The present invention relates to a remote controller, and more particularly to a remote controller with an added feature for prevention of runaway of the controller's control processing unit.
In the prior art, the remote controller was used to control TV and VTR and the like. The remote controller is provided with a CPU and a key matrix as an input means. Such remote controller is driven by a battery.
FIG. 1 is a circuit diagram illustrative of a circuit configuration of the conventional remote controller. An oscillation circuit 1 is provided for generating a basic clock signal CLK. A read only memory ROM 4 is provided for storing control programs. A key matrix 10 is provided. A key source circuit 3 is provided to be connected to the key matrix 10. A key return circuit 9 is provided to be connected to the key matrix 10. A central processing unit CPU 5 is provided to be connected to the read only memory ROM 4 for inputting address signals PC into the read only memory ROM 4 and fetching output signals DAT from the read only memory ROM 4. The central processing unit CPU 5 is also connected to the oscillation circuit 1 for inputting a stop signal STOP into the oscillation circuit 1 and fetching clock signal CLK from the oscillation circuit 1. The central processing unit CPU 5 is also connected to an output port 2 for feeding a remote control signal REM to the output port 2. The central processing unit CPU 5 is also connected to the key source circuit 3 for supplying a set signal SET into the key source circuit 3. The central processing unit CPU 5 is also connected to the key return circuit 9 via a data bus 8 for fetching data from the key return circuit 9. A pull-up resistor 6 and a capacitor 7 are connected in series between a high voltage power line and a ground line. An intermediate point between the pull-up resistor 6 and the capacitor 7 is connected to the oscillation circuit 1 and the central processing unit CPU 5 for generating a reset signal RESN when power is input and supplying the reset signal RESN to both the oscillation circuit 1 and the central processing unit CPU 5.
When the power is input, then the reset signal RESN remains at a low level until the capacitor 7 is charged up by the pull-up resistor 6 so as to reset the oscillation circuit 1 and the central processing unit CPU 5. Thereafter, the central processing unit CPU 5 receives the clock signal CLK from the oscillation circuit 1 thereby inputting address signals PC into the read only memory ROM 4. The read only memory ROM 4 reads out data stored in a designated address by the received address signal PC for subsequently feeding the data as the data signals DAT to the central processing unit CPU 5. The central processing unit CPU 5 receives the data signals DAT from the read only memory ROM 4 and then supplies the set signal SET to the key source circuit 3 for setting operations of the key source circuit 3. as well as supplies the stop signal STOP to the oscillation circuit 1 for stopping the operation of the oscillation circuit 1. Subsequently, the central processing unit CPU 5 enters a stand-by state.
FIG. 2 is a circuit diagram illustrative of the key matrix 10, the key source circuit 3 and the key return circuit 9. The key source circuit 3 comprises a plurality of n-channel transistors 31, 32 and 33, each of which has a gate connected to the central processing unit CPU 5 for receiving the set signal SET, a drain connected to the ground line and a source connected to the row of the key matrix 10. The key return circuit 9 comprises a plurality of pull-up resistors 91, 92 and 93, each of which has one side connected to the power line and the opposite side connected to the column of the key matrix 10 and the central processing unit CPU 5. If any one of the keys in the key matrix 10 is pushed on, then the one of the transistors 31, 32 and 33 connected to the selected key is connected via the selected key to the one of the pull-up resistors 91, 92 and 93. At this time, if any one of the key data is changed from a high level to a low level and the key data is fed to the central processing unit CPU 5, then the central processing unit CPU 5 is released from the stand-by state to generate the remote control signal REM on the basis of the data DAT from the read only memory ROM 4 and the clock signal CLK from the oscillation circuit 1. The generated remote control signal REM is fed from the central processing unit CPU 5 into the output port 2.
The remote controller described above is designed to be driven by the battery. After the power was input, then the reset signal RESN has was input into the central processing unit CPU 5 and the oscillation circuit 1 until the capacitor 7 is charged up by the pull-up resistor 6, during which the capacitor 7 remains charged. For this reason, so long as the battery is charged, the reset operation does not take place whereby the output from the read only memory ROM 4 varies due to a variation of power due to external noises and elimination of infrared laser emitted diode. The variation in the output from the read only memory ROM 4 may cause runaway of the central processing unit CPU 5.
Further if the power voltage is low which is critical for operational limitation, then any variation in voltage of the power is likely to appear. If the power voltage is dropped under the critical level for operational limitation, this causes the runaway of the central processing unit CPU 5. If the runaway of the central processing unit CPU 5 was once caused, then the runaway of the central processing unit CPU 5 will remain even after the power voltage is raised again above the critical level for operational limitation.
Furthermore, if the battery fails and is exchanged, since the capacitor is provided between the power line and the ground line for keeping the data it is possible that the power voltage will recover before the power voltage is dropped to the ground voltage. In summary, in this case, it is difficult to reset the central processing unit CPU 5 and the oscillation circuit 1 by the reset signal RESN, resulting in that the runaway remains.
In the above circumstances, it is required to develop a remote controller capable of releasing within a short time the central processing unit CPU 5 from runaway caused by a variation of the power voltage and external noises.